The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, the present invention is directed to an insulated gate field effect transistor of a thin film type formed on an insulating surface which may be a surface of an insulating substrate such as glass or an insulating film such as silicon oxide formed on a silicon wafer. Specifically, the present invention is applicable to a manufacture of a TFT (thin film transistor) formed on a glass substrate of which glass transition temperature (which is also called distortion point or distortion temperature) is 750° C. or lower.
The semiconductor device manufactured in accordance with the present invention is applicable to a driving circuit for an active matrix device such as a liquid crystal display or an image sensor, or a three dimensional integrated circuit.
TFTs have been well known to drive an active matrix type liquid crystal device or an image sensor. specifically, instead of amorphous TFTs having an amorphous silicon as an active layer thereof, crystalline Si TFTs have been developed in order to obtain a higher field mobility. FIGS. 6A-6F are cross sections showing a manufacturing method of a TFT in accordance with a prior art.
Referring to FIG. 6A, a base film 602 and an active layer 603 of crystalline silicon are formed on a substrate 601. An insulating film 604 is formed on the active layer using silicon oxide or the like.
Then, a gate electrode 605 is formed from phosphorous doped polysilicon, tantalum, titanium, aluminum, etc. With this gate electrode used as a mask, an impurity element (e.g. phosphorous or boron) is doped into the active layer 603 through an appropriate method such as ion-doping in a self-aligning manner, thereby, forming impurity regions 606 and 607 containing the impurity at a relatively lower concentration and therefore having a relatively high resistivity. These regions 606 and 607 are called a high resistivity region (HRD: High Resistivity Drain) by the present inventors hereinafter. The region of the active layer below the gate electrode which is not doped with the impurity will be a channel region. After that, the doped impurity is activated using laser or a heat source such as a flush lamp. (FIG. 6B)
Referring to FIG. 6C, an insulating film 608 of silicon oxide is formed through a plasma CVD or APCVD (atmospheric pressure CVD), following which an anisotropic etching is performed to leave an insulating material 609 adjacent to the side surfaces of the gate electrode as shown in FIG. 6D.
Then, using the gate electrode 605 and the insulating material 609 as a mask, an impurity element is again added into a portion of the active layer 603 by an ion doping method or the like in a self-aligning manner, thereby, forming a pair of impurity regions 610 and 611 containing the impurity element at a higher concentration and having a lower resistivity. Then, the impurity element is again activated using laser or flush lamp. (FIG. 6E)
Finally, an inter layer insulator 612 is formed on the whole surface, in which contact holes are formed on the source and drain regions 610 and 611. Electrode/wirings 613 and 614 are then formed through the contact holes to contact the source and drain regions. (FIG. 6F)
The foregoing process was achieved by copying the old LDD technique for a conventional semiconductor integrate circuit and this method has some disadvantages for a thin film process on a glass substrate as discussed below.
Initially, it is necessary to activate the added impurity element with laser or flush lamp two times. For this reason, the productivity is lowered. In the case of a conventional semiconductor circuit, the activation of an impurity can be carried out by a heat annealing at one time after completely finishing the introduction of the impurity.
However, in the case of forming TFTs on a glass substrate, the high temperature of the heat annealing tends to damage the glass substrate. Therefore, the use of laser annealing or flush lamp annealing is necessary. However, these annealing is effected on the active layer selectively, that is, the portion of the active layer below the insulating material 609 is not annealed, for example. Accordingly, the annealing step should be carried out at each time after an impurity doping is done.
Also, it is difficult to form the insulating material 609. Generally, the insulating film 608 is as thick as 0.5 to 2 μm while the base film 602 on the substrate is 1000-3000 Å thick. Accordingly, there is a danger that the base layer 602 is unintentionally etched and the substrate is exposed when etching the insulating film 608. As a result, a production yield can not be increased because substrates for TFTs contain a lot of elements harmful for silicon semiconductors.
Further, it is difficult to control the thickness of the insulating material 609 accurately. The anisotropic etching is performed by a plasma dry etching such as a reactive ion etching (RIE). However, because of the use of a substrate having an insulating surface as is different from the use of a silicon substrate in a semiconductor integrated circuit, the delicate control of the plasma is difficult. Therefore, the formation of the insulating material 609 is difficult.
Since the above HRD should be made as thin as possible, the above difficulty in precisely controlling the formation of the insulating material 609 makes it difficult to mass produce the TFT with a uniform quality. Also, the necessity of performing the ion doping twice makes the process complicated.